1. Field of the Invention
This invention relates to a circuit for troubleshooting and diagnosing an asynchronous microprocessor bus.
2. Background Art
The asynchronous bus protocol defines an environment where new bus operations start only after an acknowledgment for the completion of the previous operation is received. This protocol defines that all bus signals that participate in the current operation must remain valid for the duration of the operation, and are negated only after the operation is acknowledged. As related to bus protocols, the operation performed on the bus is usually termed a bus cycle.
The cycle can complete successfully or unsuccessfully, wherein one of two signals will be asserted to acknowledge the cycle. An acknowledge (ACK) signal will be asserted to signal a successful cycle, while a not acknowledge (NAK) signal will be asserted to signal an unsuccessful cycle. ACK an NAK signals are mutually exclusive, and until one is received, all bus signals that participate in the bus cycle remain asserted.
When a bus cycle is acknowledged with either an ACK or NAK signal, the microprocessor completes its bus access operation, and negates all bus signals that participated in the bus cycle.
Comparing pairs of data to determine the validity of data paths is a well known method for testing computer systems. This previously known method for testing bus interfaces at true operating speed is executed by performing data transfers to a memory device over the bus, reading it back from the memory device, and then comparing the two sets of data. The transfers are performed by executing test routines that reside on the device under test, which include a microprocessor and the asynchronous bus interface logic. The testing of the device under test in a system environment was actually performed by the device under test itself, comparing written data to read data. Thus, each comparison included two distinct bus cycles: a write cycle and a read cycle.
During a write cycle, the computer selected a memory device by placing its address on the addressing lines of the bus, and then sending a data pattern over the bus and writing it to the memory device. During the read cycle, the same device was re-selected, and the data it contained was read. After the read cycle was complete, the data read was verified to be identical to the test pattern that was sent over the bus.
However, since the validity of the write cycle was not verified until after the read cycle was completed, a faulty signal for that cycle would have been removed from the bus. Thus, when trying to fix the device, the failure has to be repeated, which was not easy, required additional test procedures, and consumed a fair amount of time. Even after the fault was duplicated, no means were available to freeze the state of the signal lines to a static level, so that scoping would be possible. Furthermore, quality assurance was suspect because even when malfunctioning, the device under test was the major part of the test apparatus, both controlling the test sequence and determining the validity of the test.
Thus, what is needed is a test module for troubleshooting and diagnosing an asynchronous microprocessor bus that reduces troubleshooting time and cost, while providing for a more comprehensive test in a system environment and at true operating speed.